In the past, semiconductor manufacturers have fabricated integrated circuits comprising a logic block coupled to a memory block. The logic block typically included a data processing unit, such as, for example, a central processing unit, a graphical processing unit, and a memory block that stores data that can be used by the data processing unit or stored within a hard drive, a storage network, or other memory devices. In some configurations, the memory block included volatile memory, nonvolatile memory, or a combination thereof. A conventional nonvolatile memory included a charge storage layer disposed over a substrate and a control gate overlying the charge storage layer. The charge storage layer may have included a floating gate layer, a nitride layer, a layer of nanocrystals or nanoclusters, or the like. The additional layers increased the costs of manufacturing the memory blocks as well as the time to manufacture the memory blocks. In addition, using additional layers increased the complexity of the manufacturing process while reducing the yields.
Some integrated circuits have memory cells that are manufactured using a single poly process in which a single layer of polysilicon is used to manufacture the gate electrodes for nonvolatile memory cells and transistors within the logic block. In these devices, separate charge storage and control gate layers are eliminated. Memory devices have been described in U.S. Pat. No. 8,409,944 B2, titled “Process of Forming an Electronic Device Including a Nonvolatile Memory Cell having a Floating Gate Electrode or a Conductive Member with Different Portions,” issued to Thierry Yao et al. on Apr. 2, 2013; U.S. Pat. No. 8,399,918 B2, titled “Electronic Device Including a Tunneling Structure,” issued to Thierry Yao et al. on Mar. 19, 2013; and U.S. Pat. No. 8,279,681 B2, titled “Method of Using a Nonvolatile Memory Cell,” issued to Thierry Yao et al. on Oct. 2, 2012.
Accordingly, it would be advantageous to have a memory cell and a method for manufacturing the memory cell. It would be of further advantage for the structure and method to be cost efficient to implement.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain n-channel or p-channel devices, or certain n-type or p-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described.